Today’s news, which comes on the heels of the company’s announcement with TSMC of its 5 nm portfolio, further strengthens Marvell’s leading data infrastructure offerings in the industry’s most advanced process geometry. The 112G 5 nm SerDes solution is part of Marvell’s industry-leading IP portfolio that addresses the full spectrum of infrastructure requirements and includes processor subsystems, encryption engines, system-on-chip fabrics, chip-to-chip interconnects, and a variety of physical layer interfaces.
Marvell’s 112G 5 nm SerDes offers breakthrough performance with the ability to operate at 112G PAM4 across channels with >40dB insertion loss, providing margin that is critical for high reliability infrastructure applications. The solution also delivers power reduction of more than 25% compared to 7 nm, enabling systems with tight thermal/power constraints and helping to drive down total cost of ownership. The power reduction of Marvell’s high-speed SerDes enables scale up of bandwidth within acutely constrained 5G applications.
Marvell will offer a complete product suite of PHYs, switches, data processor units (DPUs), custom server processors, controllers, accelerators and custom ASICs in 5 nm, delivering end-to-end interoperable infrastructure solutions. This interoperability between Marvell components will allow customers to significantly reduce their product development and validation cycle time, and time-to-market.
For Marvell’s ASIC customers, this IP further enhances the industry’s most comprehensive offering for leading-edge custom solutions. The Marvell ASIC business unit is engaged with customers across multiple markets looking to take advantage of this first-to-market proven silicon with differentiated power, performance, and area. These designs will lead the industry in bandwidth density.
“Our new 112G 5 nm SerDes solution, with its industry-leading power, performance and area metrics is a true game changer and will help scale data infrastructure to meet growing interconnect requirements,” said Sandeep Bharathi, senior vice president of Central Engineering at Marvell. “System performance is typically limited by bandwidth and power in most infrastructure applications, and our new 112G solution in 5 nm addresses this by doubling the bandwidth, while reducing the overall I/O power.”
“We are excited to bring this proven 112G SerDes to our custom ASIC partners looking for the highest throughput at the lowest power in the industry. Our customers in multiple markets have confirmed for us that this IP exceeds their system requirements for performance and power consumption,” said Kevin O’Buckley, vice president and general manager of the ASIC BU at Marvell. “Leveraging this 5 nm SerDes IP across our Marvell platform allows our customers to build entire interoperable data center, wireless and wired networking systems using Marvell standard products, customized standard products and full custom ASIC solutions.”
“Marvell is clearly staking out a leadership position as the market rapidly transitions to 100G serial,” said Alan Weckel, founder and technology analyst of 650 Group. “We expect that 100G serial will be a foundational speed similar to 10G and 25G, and an important technology in enabling the evolution of data center architectures optimized for emerging workloads such as AI and machine learning. By bringing this 112G 5 nm SerDes solution to the industry now, Marvell is accelerating the deployment of next generation infrastructure and raising the bar on performance capabilities across compute, networking and storage.”